The present invention relates to a circuit for synchronizing an external video signal with an internal sampling signal, especially a synchronizing circuit for a video signal and a sampling clock suitable to convert the video signal to a digital signal in an image processing apparatus.
In a circuit for digitalizing an input video signal and supplying a digitalized video signal to an image processing circuit, there occur some data disturbances, for example, bit errors of the digitalized video signal, caused by a phase or frequency shift between the digitalized video signal and a sampling clock generated in the circuit. These disturbances have a remarkable influence on characters displayed on computer terminals. Namely, the characters displayed on a cathode ray tube (hereinafter, CRT) are represented by a small dot matrix, for example, 16.times.16 or 24.times.24 dots, which are determined by the CRT resolution. Therefore, there is some possibility that the characters may become indistinct even in case of one dot deviation.
Japanese Laid Open Patent Application No. 16288/83 (Tokkai Sho 58-16288) discloses apparatus for resolving the above mentioned problem.
FIG. 1 shows a block diagram of the prior art. A horizontal synchronizing signal 120 supplied from a transmission side is input to an inverter 122 and a D terminal of a flip flop 123. The inverter 122 inverts a supplied "1" level and provides a "0" level to the delay circuit 124. The delay circuit 124 delays the "0" level by periods TD, 2TD, . . . , 8TD and supplies them to flip flops 125. In this state, when a sampling clock signal 121 is supplied to a CK terminal of the flip flop 123, the "1" level provided on the D terminal thereof is latched and a leading edge at a Q terminal is supplied to a CK terminal of the flip flops 125. The sampling clock signal 121 has the same frequency as one of the transmission side. The flip flops 125 latch signals provided on input terminals D0 to D7 at the leading edge of the Q terminal, and outputs them via corresponding terminals Q0 to Q7. A priority encoder 126 encodes signals supplied to terminals P0 to P7, when a "0" level signal is supplied to an EI terminal. The encoder 126 outputs a code signal corresponding to a differential period between the sampling clock signal 121 and the horizontal synchronizing signal 120.
Further, a video signal 129 provided from the transmission side is delivered to a delay circuit 128. The delay circuit 128 delays the video signal 129 by a plurality of delay times and supplies it to D terminals D0 to D7 of a multiplexer 127. The multiplexer 127 receives the code signal corresponding to the differential period and selects the delayed video signal in response to the code signal. As a result, a phase difference between the video signal 129 and the sampling clock signal 121 is compensated.
As mentioned above in detail, the phase error between the supplied horizontal synchronizing signal and the inner generated sampling clock signal is detected, and the phase of the supplied video signal is corrected in response to the phase error, so that it becomes possible to sample the supplied video signal accurately without dot errors.
However, in this prior art arrangement, since the horizontal synchronizing signal is used for detecting the phase error between the supplied video signal and the sampling clock signal, it is necessary that a phase relation between the video signal and the horizontal synchronizing signal is constant.
In a general video apparatus using a CRT, the phase difference between the horizontal synchronizing signal and the video signal is not compensated. As a result, in this prior art arrangement, there remain some possibilities to cause dot errors in a displayed picture. Namely, in case of applying the above mentioned prior art to each apparatus having an intrinsic phase difference between the horizontal synchronizing signal and the video signal, it is necessary to set a predetermined delay amount of the video signal to the horizontal synchronizing signal in each apparatus.